Embodiments of the present disclosure relate to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices having buried metal silicide layers and methods of fabricating the same.
As digital home appliances become smaller in size and mobile systems become wide-spread, semiconductor devices employed in the digital home appliances and the mobile systems have been continuously scaled down. Attempts to increase the device integration density in dynamic random access memory (DRAM) devices or flash memory devices including memory cells have typically resulted in the reduction of areas (planar areas) that the memory cells occupy. In general, a unit memory cell of the DRAM devices includes a cell transistor and a cell capacitor. The DRAM cell transistors may be formed in and/or on a semiconductor substrate and the DRAM cell capacitors may be stacked on the DRAM cell transistors to increase the integration density of the DRAM devices.
The DRAM cell transistors may be electrically connected to the DRAM cell capacitors through storage node contact plugs which are disposed between source regions of the DRAM cell transistors and bottom electrodes of the DRAM cell capacitors. Further, drain regions of the DRAM cell transistors may be electrically connected to bit lines through bit line contact plugs, and gate electrodes of the DRAM cell transistors may be electrically connected to word lines. Therefore, the bit lines and the word lines for transmitting electric signals may be disposed between the DRAM cell transistors and the DRAM cell capacitors. Thus, there may be some limitations in increasing the cell capacitance due to the presence of the bit lines and the word lines. Moreover, most of the DRAM cell transistors may be formed to have a planar configuration. In such a case, if a width of the word lines is reduced to increase the integration density of the DRAM devices, electrical resistance of the word lines may increase. As a result, RC delay time of the word lines may increase to degrade the performance of the DRAM devices. In addition, if the planar type cell transistors are scaled down, leakage current of the planar type cell transistors may abruptly increase to degrade the cell characteristics of the DRAM devices. Accordingly, vertical transistors have been proposed to solve or overcome the disadvantages of the planar transistors.